RSA Accelerator

Hardware-Accelerated RSA Encryptor implemented on FPGA using Montgomery’s Method. The accelerator is optimized for 256-bit messages and leverages pipelining and parallelism to maximize throughput.

In a test run with 4,000 unique messages, the chip completed encryption and decryption of all messages in just 68 milliseconds.

This project was part of a digital design course at NTNU and was benchmarked as the 13th fastest design of all time.